Copper has become the metal of choice over aluminum in the fabrication of integrated circuits because it has a lower resistance than aluminum and allows for the scaling down of devices. Despite its advantages, the use of copper in interconnection/interconnect structures poses several special problems that did not exist with the use of aluminum. One such problem is the formation of copper hillocks. Copper is a soft metal and has a much higher expansion coefficient than aluminum, so that it expands significantly when heated under typical temperatures used in semiconductor processing. Copper hillocks are a result of this expansion. Copper interconnect lines are typically formed by a dual damascene process wherein trench and via openings are etched into a dielectric layer and are then filled with copper. A barrier layer to prevent the migration of copper is typically formed in the trench and via openings before they are filled with copper. Copper within the trench and via openings is constrained on three sides by the barrier layer, and when heated, it can only expand upwards or along the copper line. Copper expands from the copper line in the form of spike-like projections, hence the name “hillocks.” The formation of copper hillocks is a serious problem because hillocks cause shorts and voids, and can cause early breakdown of the semiconductor devices.
FIG. 1A illustrates a planarized copper dual damascene structure. The dual damascene structure has a first copper line 110 formed within a barrier layer 115, which is formed within a trench in a first dielectric layer 120. Copper hillocks such as 125 typically begin to form before any subsequent processing due to pent-up thermal expansion energy in the copper. FIG. 1B illustrates an interconnect structure 130 after a second dielectric layer 135 (typically SiN), which will serve as an etch stop layer, has been formed over the first copper line 110. A silicon nitride deposition is typically performed at about 400° C., a temperature at which copper will expand significantly and form copper hillocks. The copper hillocks 125 that already existed before the silicon nitride deposition will grow larger, and additional copper hillocks such as 145, will form during the deposition.
FIG. 1C illustrates the formation of a second interconnect structure 150, which includes a second copper line 165 in a third dielectric layer 155, over the second dielectric layer 135. The heat and pressure exerted on the first interconnect structure 130 during the formation of the third dielectric layer 155 and subsequent layers can cause the copper hillocks to grow even larger. The third dielectric layer 155 is typically carbon or fluorine doped silicon oxide that is deposited at temperatures of around 450° C. to 480° C. These temperatures will cause significant expansion of the copper and growth of hillocks. The growth of large copper hillocks can cause a short 160 between the first copper line 110 and the second copper line 165. Also, the formation of hillocks can cause a void 170 to form within the first copper line 110.
Multiple methods for solving the problem of copper hillocks have been explored. One explicit solution is to reduce the temperatures used in the processing. Copper hillocks typically form at temperatures above 150° C. Therefore, processing temperatures can be kept lower than this temperature to prevent hillocks from forming. However, this method is not effective in producing optimal semiconductor devices because low temperatures produce materials having inferior qualities such as lower density and less homogeneity.
Another solution to prevent the formation of copper hillocks is to anneal the copper before the step of chemical mechanical polish (CMP) of the copper. The intent of this anneal is to expend most of the thermal expansion energy of the copper into the formation of copper hillocks that can then be polished away during the CMP step. By expending most or all of the thermal expansion energy of the copper during this pre-CMP anneal, hillocks are less likely to form at a later point. Drawbacks of this solution are that extra process steps and thermal budget are required, and there is a risk of forming voids in the copper interconnect structures due to the hillock growth.
Yet another solution to reduce hillocks is to use two-step plating for the formation of copper layers. In a two-step plating process, a first copper layer is plated followed by an annealing. A second copper layer, which is virtually a repetition of the first copper layer, is then plated on the first copper layer. This method slightly improves the copper surface with smaller hillock sizes. However, the amount of hillocks may be increased, and thermal budget is also increased.